Tesla is seeking a highly skilled and experienced Static Timing Analysis (STA) Engineer to join our dynamic team. As an STA Engineer, you will play a critical role in the development of System-on-Chip (SoC) designs, ensuring the successful tape-out of complex integrated circuits. The ideal candidate will have a proven track record of delivering high-quality designs with excellent understanding of micro-architecture, timing methodologies and physical design concepts.
What You’ll Do- Perform static timing analysis and optimization to ensure design closure and meet performance requirements
- Collaborate with the design and physical implementation teams to develop timing constraints and methodologies for achieving optimal performance
- Conduct feasibility studies to evaluate design trade-offs and propose solutions to improve timing and power
- Identify and resolve timing issues, including setup and hold violations, clock domain crossing, and other timing-related problems
- Work closely with the verification team to analyze and resolve timing-related functional issues
- Develop and maintain timing models and libraries for accurate and efficient timing analysis
- Drive and support STA-related methodologies, flows, and tool enhancements to improve productivity and quality of results
- Stay up to date with the latest industry trends and best practices in STA and related fields
- Understanding of ECO flows and eco generation methodologies
- Experience with timing constraints development and validation
- Bachelor's degree in a related field, or equivalent experience
- Proven track record of successful tape-outs and meeting performance targets
- Strong understanding of micro-architecture and physical design concepts
- Proficient in using industry-standard EDA tools for STA, such as PrimeTime, Tempus, or equivalent
- Familiarity with scripting languages such as Tcl or Perl for automation
- Experience with advanced process technologies (e.g., FinFET, 7nm, 5nm) is preferred
- Knowledge of low-power design techniques and clock domain crossing analysis is preferred
- Familiarity with formal verification techniques and tools is preferred
- Experience with high-speed interface protocols (e.g., PCIe, DDR, Ethernet) is preferred
- Understanding of statistical timing analysis and variation-aware design methodologies is preferred